Expanding into the third dimension let chip manufacturers continue shrinking transistors to boost speed with no power leaks. However, chip stacking is limited by wiring-related problems. Today's interconnects do not run through the silicon itself but go millimeters around it, impeding speedy signaling and increasing power consumption along the way. 2-D (horizontal) real estate is also valuable. Even the thinnest interconnects must still be packed along the edges of a chip, imposing strict limits on how many input/output connections the chip can handle. Consequently, going vertical (3-D) by connecting one chip to another with lines that go straight through the silicon—commonly known as through-silicon vias (TSVs)—offers the numerous potential benefits. In particular, more connections can be packed side by side using much slimmer wires. Going through chips instead of around the side also reduces the length of interconnects from millimeters to microns or even less—as thin as individual wafers can be produced. It has been estimated that the switch to vertical interconnects may reduce power consumption in half, increase bandwidth by a factor of eight, and shrink memory stacks by some 35 percent.
As several hundreds of thousands of TSVs in a single package provide power/ground, clock, functional signals, as well as test access to logic blocks of different layers of the device, they become not only the key components of 3-D ICs but also make up a crucial test infrastructure. In order to form TSVs, one has to etch deep, narrow holes into a silicon wafer and then fill them with a nearly flawless layer of insulating material and then copper. But as a wafer heats up, copper expands at more than five times the rate that silicon does, exerting stress that can crack the wafer and render it useless. Because of such imperfect etching, ragged wafer surface, and potential wafer misalignments, certain TSVs in one wafer after thinning and polishing might not be completely exposed or aligned with their counterparts on the other wafer. Since the bonding quality of TSVs depends on the winding level of the thinned wafer as well as the surface roughness and cleanness of silicon dies, defective TSVs tend to occur in clusters, though even a single TSV defect between any two layers can void the entire chip stack, reducing the overall yield.
Numerous novel testing schemes for 3-D ICs, especially for those with TSV-based interconnects, have been proposed. Virtually all of them are motivated by 3-D processing steps such as thinning, alignment, or stacking that introduce new defects including voids, peeling, delamination, chipping, and cracking. These mechanisms can lead to both strong/weak opens and strong/weak shorts causing either no signal propagation through vias or propagation with a degraded amplitude/slew. Since maintaining the high signal quality is one of the primary objectives of 3-D system integration, it becomes imperative to properly identify defective TSVs and replace them, if needed, with spare fault-free ones by deploying appropriate diagnostic and subsequently self-repairing and/or rerouting strategies. It is worth noting that the pre-bond testing of TSVs is of particular difficulty, as the existing probe technologies may be unable to make contact with thousands of individual TSVs. Thus, there are methods allowing a probe card to contact TSVs without the need for probe pads. Moreover, several conventional techniques suffer from the fact that TSVs are single-ended at this stage of test. The existing methods use therefore either on-chip TSV monitoring in conjunction with a sense amplification technique or some forms of TSV network probing.
The post-bond stack testing ensures that a 3-D IC works as intended and no new defects are introduced during bonding and related operations. Many TSV test methods proposed for this phase include different types of BIST and scan-based schemes that target, in particular, TSV crosstalk faults. A cellular automata-based TSV test scheme has also been proposed. Other solutions aim at deriving test sequences for TSVs based on fault models at electrical levels. Some fault diagnosis techniques use thermography and electron microscopy with dispersive X-ray spectroscopy. A test access architecture allows both pre-bond die testing and post-bond stack testing by deploying a modular scheme, in which various dies, embedded IP cores, and TSV-based interconnects are tested as separate units to allow optimization of the IEEE 1500 standard-based 3-D IC test flow. As TSVs may aggravate routing congestions, it is often necessary to reduce their role in test. It has been observed that by varying connection orders of wrapper chain components, e.g., scan chains and I/O cells, the TSVs involved may vary significantly. One of the proposed structures can detect the signal degradation through vias due to resistive shorts and variations in resistance due to weak open and/or bonding resistance. For TSVs with moderate signal degradations, it reconfigures itself as a signal recovery circuit to maintain its quality. Many TSVs implemented in 3-D DRAMs are prone to open defects and couplings as shown by simulation studies modeling the faulty behavior of TSV opens as a key part of fault diagnosis. A semi-automated design flow for 3-D networks-on-chip uses a defect-tolerance scheme to increase the yield of stacked chips by starting from an accurate physical and geometrical model of TSVs. Other schemes either employ an IEEE 1500 compatible testing methodology for TSVs-based interconnects or are designed so that the overall test application time for 3-D ICs is optimized. A socket solution deploys a customized contactor for direct testing of TSVs and micro-bump arrays. It enables creation of good TSV dies for high yield stacking and good TSV stacks for shipment to system assemblers to achieve high yield assembly.
Although, as shown above, defect mechanisms may vary, some of the resulting TSV faults are similar to failures typically affecting wiring networks. As a result, one could leverage, to some extent, the existing test generation methods by assuming full controllability at the interconnect inputs and full observability at the interconnect outputs, as done, for example, in the boundary-scan architecture. Such algorithms detect most of the faults through test patterns that grow only logarithmically with the number of wires. This disclosure introduces a new scan-based test architecture for TSVs along with the corresponding post-bond test generation techniques capable of detecting and accurately identifying variety of single and multiple faults for TSVs in 3-D stacked ICs.